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LTC2400 24-Bit Power ADC in SO-8
November 1998
FEATURES
s s s s s s
DESCRIPTIO
s s
s s
s s
24-Bit ADC in SO-8 Package 4ppm INL, No Missing Codes 4ppm Full-Scale Error 0.5ppm Offset 0.3ppm Noise Internal Oscillator--No External Components Required 110dB Min, 50Hz/60Hz Notch Filter Single Conversion Settling Time for Multiplexed Applications Reference Input Voltage: 0.1V to 0.9 x VCC Live Zero--Extended Input Range Accommodates 12.5% Overrange and Underrange Single Supply 2.7V to 5.5V Operation Low Supply Current (200A) and Auto Shutdown
The LTC(R)2400 is a 2.7V to 5.5V micropower 24-bit converter with an integrated oscillator, a 4ppm INL and 0.3ppm RMS noise. It uses delta-sigma technology and it provides single cycle settling time for multiplexed applications. Through a single pin the LTC2400 can be configured for better than 110dB rejection at 50Hz or 60Hz 2%, or it can be driven by an external oscillator for a user defined rejection frequency in the range 1Hz to 120Hz. The internal oscillator requires no external frequency setting components. The converter accepts any external reference voltage from 0.1V to 0.9 x VCC. With its extended input conversion range of -12.5% VREF to 112.5% VREF the LTC2400 smoothly resolves the offset and overrange problems of preceding sensors or signal conditioning circuits. The LTC2400 communicates through a flexible 3-wire digital interface which is compatible with SPI and MICROWIRETM protocols.
, LTC and LT are registered trademarks of Linear Technology Corporation. MICROWIRE is a trademark of National Semiconductor Corporation.
APPLICATIO S
s s s s s s s s
Weight Scales Direct Temperature Measurement Gas Analyzers Strain-Gage Transducers Instrumentation Data Acquisition Industrial Process Control 6-Digit DVMs
TYPICAL APPLICATIO
2.7V TO 5.5V 1F VCC FO
Total Unadjusted Error vs Output Code
10 8
VCC
LINEARITY ERROR (ppm)
= INTERNAL OSC/50Hz REJECTION = EXTERNAL CLOCK SOURCE = INTERNAL OSC/60Hz REJECTION
6 4 2 0 -2 -4 -6 -8
REFERENCE VOLTAGE 0.1V TO 0.9 x VCC ANALOG INPUT RANGE -0.12VREF TO 1.12VREF
VREF
SCK 3-WIRE SPI INTERFACE
VIN GND
SDO CS
2400 TA01
-10 0 8,338,608 OUTPUT CODE (DECIMAL) 16,777,215
2400 TA02
Specifications on this data sheet are preliminary only, and subject to change without notice. Contact the manufacturer before finalizing a design using this part.
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VDD = 5V VREF = 4.5V TA = 25C FO = LOW
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LTC2400
ABSOLUTE
(Notes 1, 2)
AXI U RATI GS
PACKAGE/ORDER I FOR ATIO
TOP VIEW VCC 1 VREF 2 VIN 3 GND 4 8 7 6 5 FO SCK SDO CS
Supply Voltage (VCC) to GND .......................- 0.3V to 7V Analog Input Voltage to GND ....... - 0.3V to (VCC + 0.3V) Reference Input Voltage to GND .. - 0.3V to (VCC + 0.3V) Digital Input Voltage to GND ........ - 0.3V to (VCC + 0.3V) Digital Output Voltage to GND ..... - 0.3V to (VCC + 0.3V) Operating Temperature Range LTC2400C................................................ 0C to 70C LTC2400I............................................ - 40C to 85C Storage Temperature Range ................. - 65C to 150C Lead Temperature (Soldering, 10 sec).................. 300C
ORDER PART NUMBER LTC2400C LTC2400I S8 PART MARKING 2400 2400I
S8 PACKAGE 8-LEAD PLASTIC SO
TJMAX = 125C, JA = 130C/W
Consult factory for Military grade parts.
CO VERTER CHARACTERISTICS
PARAMETER Resolution (No Missing Codes) Integral Nonlinearity Offset Error Offset Error Drift Full-Scale Error Full-Scale Error Drift Total Unadjusted Error Output Noise Normal Mode Rejection 60Hz 2% Normal Mode Rejection 50Hz 2% CONDITIONS 2.5V VREF VCC, (Note 5) VREF = 2.5V (Note 6) VREF = 4.5V (Note 6) 2.5V VREF 0.9 x VCC 2.5V VREF 0.9 x VCC 2.5V VREF 0.9 x VCC 2.5V VREF 0.9 x VCC VREF = 2.5V VREF = 4.5V VIN = 0V (Note 13) (Note 7) (Note 8)
(Notes 3, 4)
MIN
q q q q q q q q q q q q q q q
TYP 2 4 0.5 0.01 4 0.04 5 10 1.5
MAX 8 15 3 10 20 30
UNITS Bits ppm of VREF ppm of VREF ppm of VREF ppm of VREF/C ppm of VREF ppm of VREF/C ppm of VREF ppm of VREF VRMS dB dB dB dB dB dB dB
24
110 110 110 110
140 140 140 140 100 110 110
Reference Input Rejection 60Hz 2% (Note 7) Reference Input Rejection 50Hz 2% (Note 8) Power Supply Rejection DC Power Supply Rejection 60Hz 2% Power Supply Rejection 50Hz 2% VREF = 2.5V, VIN = 0V VREF = 2.5V, VIN = 0V, (Note 7) VREF = 2.5V, VIN = 0V, (Note 8)
A ALOG I PUT A D REFERE CE
SYMBOL VIN VREF CS(IN) CS(REF) IIN IREF PARAMETER Input Voltage Range Reference Voltage Range Input Sampling Capacitance Reference Sampling Capacitance Input Leakage Current Reference Leakage Current CONDITIONS (Note 14)
(Note 3)
MIN
q q q q
TYP
MAX 1.125 * VREF 0.9 x VCC
UNITS V V pF pF
- 0.125 * VREF 0.1 10 15 1 1
VIN = 0V, CS = VCC VREF = 5V, CS = VCC
q q
10 10
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nA nA
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LTC2400 DIGITAL I PUTS A D DIGITAL OUTPUTS
SYMBOL VIH VIL VIH VIL IIN IIN CIN CIN VOH VOL VOH VOL IOZ PARAMETER High Level Input Voltage CS, FO Low Level Input Voltage CS, FO High Level Input Voltage SCK Low Level Input Voltage SCK Digital Input Current CS, FO Digital Input Current SCK Digital Input Capacitance CS, FO Digital Input Capacitance SCK High Level Output Voltage SDO Low Level Output Voltage SDO High Level Output Voltage SCK Low Level Output Voltage SCK High-Z Output Leakage SDO (Note 9) IO = - 800A IO = 1.6mA IO = - 800A (Note 10) IO = 1.6mA (Note 10) CONDITIONS 2.7V VCC 5.5V 2.7V VCC 3.3V 4.5V VCC 5.5V 2.7V VCC 5.5V 2.7V VCC 5.5V (Note 9) 2.7V VCC 3.3V (Note 9) 4.5V VCC 5.5V (Note 9) 2.7V VCC 5.5V (Note 9) 0V VIN VCC 0V VIN VCC (Note 9)
q q q q q q q q q q q q q
POWER REQUIRE E TS
SYMBOL VCC ICC PARAMETER Supply Voltage Supply Current Conversion Mode Sleep Mode
TI I G CHARACTERISTICS
SYMBOL fEOSC tHEO tLEO tCONV PARAMETER External Oscillator Frequency Range External Oscillator High Period External Oscillator Low Period Conversion Time
fISCK
Internal SCK Frequency
UW
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(Note 3)
MIN 2.5 2.0 0.8 0.6 2.5 2.0 0.8 0.6 -10 -10 10 10 VCC - 0.5V 0.4V VCC - 0.5V 0.4V 10 10 10 TYP MAX UNITS V V V V V V V V A A pF pF V V V V A
(Note 3)
CONDITIONS
q q
MIN 2.7
TYP
MAX 5.5
UNITS V A A
CS = 0V (Note 12) CS = VCC (Note 12)
200 20
UW
(Note 3)
CONDITIONS
q q q
MIN 2.56 0.5 0.5
TYP
MAX 307.2 390 390
UNITS kHz s s ms ms ms kHz kHz
FO = 0V FO = VCC External Oscillator (Note 11) Internal Oscillator (Note 10) External Oscillator (Notes 10, 11)
q q q
130.66 133.33 136 156.80 160 163.20 20480/fEOSC (in kHz) 19.2 fEOSC/8
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LTC2400
TI I G CHARACTERISTICS
SYMBOL DISCK fESCK tLESCK tHESCK tDOUT_ISCK tDOUT_ESCK t1 t2 t3 t4 tKQMAX tKQMIN t5 t6 PARAMETER Internal SCK Duty Cycle External SCK Frequency Range External SCK Low Period External SCK High Period Internal SCK 32-Bit Data Output Time External SCK 32-Bit Data Output Time CS to SDO Low Z CS to SDO High Z CS to SCK CS to SCK SCK to SDO Valid SDO Hold After SCK SCK Set-Up Before CS SCK Hold After CS (Note 5) (Note 10) (Note 9)
The q denotes specifications which apply over the full operating temperature range; all other limits and typicals apply to TA = 25C. Note 1: Absolute Maximum Ratings are those values beyond which the life of the device may be impaired. Note 2: All voltage values are with respect to GND. Note 3: VCC = 2.7 to 5.5V unless otherwise specified. Note 4: Internal Conversion Clock source with the FO pin tied to GND or to VCC or to external conversion clock source with fEOSC = 153600Hz unless otherwise specified. Note 5: Guaranteed by design, not subject to test. Note 6: Integral nonlinearity is defined as the deviation of a code from a straight line passing through the actual endpoints of the transfer curve. The deviation is measured from the center of the quantization band. Note 7: FO = 0V (internal oscillator) or fEOSC = 153600Hz 2% (external oscillator). Note 8: FO = VCC (internal oscillator) or fEOSC = 128000Hz 2% (external oscillator).
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UW
(Note 3)
CONDITIONS (Note 10) (Note 9) (Note 9) (Note 9) Internal Oscillator (Notes 10, 12) External Oscillator (Notes 10, 11) (Note 9)
q q q q q q q q q q q q q q
MIN 45 250 250 1.64
TYP
MAX 55 2000
UNITS % kHz ns ns
1.67 1.7 256/fEOSC (in kHz) 32/fESCK (in kHz) 50 50 50 150
ms ms ms ns ns ns ns ns ns ns
0 0 0 50 15 50
50
ns
Note 9: The converter is in External SCK mode of operation such that the SCK pin is used as digital input. The frequency of the clock signal driving SCK during the Data Output is fESCK and is expressed in kHz. Note 10: The converter is in Internal SCK mode of operation such that the SCK pin is used as digital output. In this mode of operation the SCK pin has a total equivalent load capacitance CLOAD = 20pF. Note 11: The external oscillator is connected to the FO pin. The external oscillator frequency, fEOSC, is expressed in kHz. Note 12: The converter uses the internal oscillator. FO = 0V or FO = VCC. Note 13: The output noise includes the contribution of the internal calibration operations. Note 14: For reference voltage values VREF > 2.5V the extended input of - 0.125 * VREF to 1.125 * VREF is limited by the absolute maximum rating of the Analog Input Voltage pin (Pin 3). For 2.5V < VREF 0.267V + 0.89 * VCC the Input Voltage Range is - 0.3V to 1.125 * VREF. For 0.267V + 0.89 * VCC < VREF VCC the Input Voltage Range is - 0.3V to VCC + 0.3V.
LTC2400
PI FU CTIO S
VCC (Pin 1): Positive Supply Voltage. Bypass to GND (Pin 4) with a 10F tantalum capacitor in parallel with 0.1F ceramic capacitor as close to the part as possible. VREF (Pin 2): Reference Input. The reference voltage range is 0.1V to 0.9 x VCC. VIN (Pin 3): Analog Input. The input voltage range is - 0.125 * VREF to 1.125 * VREF. For VREF > 2.5V the input voltage range may be limited by the pin absolute maximum rating of - 0.3V to VCC + 0.3V. GND (Pin 4): Ground. Shared pin for analog ground, digital ground, reference ground and signal ground. Should be connected directly to a ground plane through a minimum length trace or it should be the single-point-ground in a single point grounding system. CS (Pin 5): Active Low Digital Input. A low on this pin enables the SDO digital output. Following each conversion the ADC automatically enters the Sleep mode and remains in this low power state as long as CS is high. A low on CS wakes up the ADC. A high on this pin disables the SDO digital output. A low-to-high transition on CS during the Data Output state aborts the data transfer and stats a new conversion. SDO (Pin 6): Three-State Digital Output. During the data output period this pin is used for serial data output. When the chip select CS is high (CS = VCC) the SDO pin is in a high impedance state. During the Conversion and Sleep periods this pin can be used as a conversion status output. The conversion status can be observed by pulling CS low. SCK (Pin 7): Bidirectional Digital. In Internal Serial Clock Operation mode, SCK is used as digital output for the internal serial interface clock during the data output period. In External Serial Clock Operation mode, SCK is used as digital input for the external serial interface. A weak internal pull-up is automatically activated in Internal Serial Clock Operation mode. FO (Pin 8): Digital input which controls the ADC's notch frequencies and conversion time. When the FO pin is connected to VCC (FO = VCC) the converter uses its internal oscillator and the digital filter first null is located at 50Hz. When the FO pin is connected to GND (FO = OV) the converter uses its internal oscillator and the digital filter first null is located at 60Hz. When FO is driven by an external clock signal with a frequency fEOSC the converter uses this signal as its clock and the digital filter first null is located at a frequency fEOSC/2560.
FU CTIO AL BLOCK DIAGRA
VCC GND
VIN

ADC SERIAL INTERFACE DECIMATING FIR
VREF
DAC
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INTERNAL OSCILLATOR AUTOCALIBRATION AND CONTROL
FO (INT/EXT)
SDO SCK NCS
2400 FD
5
LTC2400
TEST CIRCUITS
VCC
SDO 1.6k CLOAD = 20pF
1.6k SDO CLOAD = 20pF
HI-Z TO VOH VOL TO VOH VOH TO HI-Z
2400 TA03
HI-Z TO VOL VOH TO VOL VOL TO HI-Z
2400 TA04
APPLICATIO S I FOR ATIO
Converter Operation Cycle
The LTC2400 operation cycle is composed of three distinct states: Conversion, Sleep and Data Output (see Figure 1). After the completion of a conversion the LTC2400 automatically enters the Sleep state and reduces its power consumption by more than an order of magnitude. The converter remains in this state as long as a logic HIGH level is detected at the CS pin. Whenever a new data point is not required the LTC2400 should be kept in this state by maintaining a logic HIGH at the CS pin.
CS = LOW SDO = LOW AND SCK DATA OUTPUT
END OF CONVERSION CONVERT SLEEP
END OF DATA OUTPUT OR CS
2400 F01
Figure 1. LTC2400 State Transition Diagram
From the Sleep state the converter will transition into the Data Output state on the first LOW to HIGH transition of the SCK pin which occurs while the CS input pin is driven LOW (the SDO output pin is also in a LOW state indicating the conversion is complete). The signal at the SCK pin can be generated internally (Internal SCK mode and SCK is an output pin) or externally (External SCK mode and SCK is an input pin). When the converter is in the Data Output state and logic HIGH is detected at the CS pin the Data Output Operation is aborted, a new conversion is started and the LTC2400
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enters the Conversion state. Even if a logic LOW is continuously maintained at the CS pin the data output is automatically terminated after the transmission of the 32nd bit of data. At this moment a new conversion is started and the LTC2400 enters the Conversion state. A detailed description of the transitions between the Sleep, Data Output and Conversion states in various conditions is contained in the Configuration Options section. The time the converter spends in each one of these three states is determined by the selected operation mode. The various options are described in Table 1. Power-Up Sequence The LTC2400 automatically enters an internal reset state whenever the power supply voltage VCC drops below approximately 2.2V. This feature is necessary in order to guarantee the integrity of the conversion result and of the Serial Interface mode selection. When the VCC voltage raises above this critical threshold the converter creates an internal power-on-reset signal with duration of approximately 0.5ms. The power-onreset signal clears all internal registers and activates the internal SCK pull-up device. After the power-on-reset delay, if the CS pin is LOW, the SCK pin is tested and the Serial Clock Operation mode is selected (internal if SDO = HIGH and external if SDO = LOW). Following the poweron-reset signal the LTC2400 starts a normal conversion cycle and follows the normal succession of states described above.
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LTC2400
APPLICATIO S I FOR ATIO
Table 1. LTC2400 State Duration
State CONVERT Operating Mode Internal Oscillator
FO = LOW (60Hz Rejection) FO = HIGH (50Hz Rejection)
External Oscillator SLEEP DATA OUTPUT Internal Serial Clock
FO = External Oscillator with Frequency fEOSC kHz FO = LOW/HIGH (Internal Oscillator) FO = External Oscillator with Frequency fEOSC kHz
External Serial Clock with Frequency fSCK kHz
Reference Voltage Range The LTC2400 can accept a reference voltage from 0V to 0.9 x VCC. The converter output noise is determined by the thermal noise of the front end circuits, and as such it will not scale with the reference voltage. Therefore, a decrease in reference voltage will not improve the converter resolution. On the other hand, a reduced reference voltage will improve the overall converter INL performance. The recommended range for the LTC2400 voltage reference is 100mV to 0.9 x VCC. Input Voltage Range The converter is able to accommodate system level offset and gain errors as well as system level overrange situations due to its extended input range. The LTC2400 converts input signals within the extended input range - 0.125V * VREF to 1.125 * VREF. For large values of VREF this range is limited by the absolute maximum voltage range of - 0.3V to (VCC + 0.3V). Beyond this range the input ESD protection devices begin to turn on and the errors due to the input leakage current increase rapidly. Because of the very low input capacitance of the VIN pin, if the VIN signal can go beyond the absolute maximum range of - 0.3V to (VCC + 0.3V) a resistor of up to 5k can be added in series with the VIN input in order to limit the
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Duration 133ms 160ms 20480/fEOSCms As Long As CS = HIGH As Long As CS = LOW But Not Longer Than 1.67ms As Long As CS = LOW But Not Longer Than 256/fEOSCms As Long As CS = LOW But Not Longer Than 32/fSCKms
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input current. In the physical layout it is important to maintain the parasitic capacitance of the connection between this series resistance and the VIN pin as low as possible, therefore the resistor should be located as close as possible to the VIN pin. The effect of the series resistance on the converter accuracy can be evaluated from the curves presented in the Typical Performance Characteristics section. In addition it is important to understand that such a series resistor will introduce a temperature dependent offset error due to the input leakage current. A 10nA input leakage current will develop a 1ppm offset error on a 500 resistor if VREF = 5V. This error has a very strong temperature dependency.
VCC + 0.3V 9/8VREF VREF ABSOLUTE MAXIMUM INPUT RANGE
1/2VREF
NORMAL INPUT RANGE
EXTENDED INPUT RANGE
0 -1/8VREF -0.3V
2400 F02
Figure 2. LTC2400 Input Range
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LTC2400
APPLICATIO S I FOR ATIO
Output Data Format
The LTC2400 serial output data stream can be up to 32 bits long. The serial data transfer can be aborted at any time as described in the Configuration Options section. A serial bit is output at the SDO pin on each falling edge of the SCK signal after the first rising edge during the Data Output state. The first four bits contain status information indicating the sign and the expanded input range condition for the input signal. Bit 31 (first output bit) is the end of conversion (EOC) indicator. This bit is available at the SDO pin during the Conversion and Sleep states whenever the CS pin is LOW. This bit is HIGH only during the Conversion and goes LOW when the conversion is complete. Bit 30 (second output bit) is not used in this implementation and is always LOW. Bit 29 (third output bit) is the conversion result sign indicator (SIG). If the input signal is 0 this bit is HIGH. If the input signal is <0 this bit is LOW. Bit 28 (forth output bit) is the extended input range (EXR) indicator. If the input is within the normal input range 0 VIN VREF this bit is LOW. If the input is outside the normal input range VIN > VREF or VIN < 0 this bit is HIGH.
Table 3. LTC2400 Output Data Format
Input Voltage VIN > 9/8 * VREF 9/8 * VREF VREF + 1LSB VREF 3/4VREF + 1LSB 3/4VREF 1/2VREF + 1LSB 1/2VREF 1/4VREF + 1LSB 1/4VREF 0 -1LSB -1/8 * VREF VIN < -1/8 * VREF B31 EOC 0 0 0 0 0 0 0 0 0 0 0 0 0 0 B30 DMY 0 0 0 0 0 0 0 0 0 0 0 0 0 0 B29 SIG 1 1 1 1 1 1 1 1 1 1 1 0 0 0 B28 EXR 1 1 1 0 0 0 0 0 0 0 0 1 1 1
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The function of these bits is summarized in Table 2.
Table 2. LTC2400 Status Bits
Input Range VIN > VREF 0 VIN VREF VIN < 0 B31 (MSB) EOC 0 0 0 B30 0 0 0 B29 SIG 1 1 0 B28 EXR 1 0 1
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The next 28 bits represent the conversion result and are output MSB first (i.e. Bit 4 is the most significant bit of the conversion result while Bit 31 is the least significant bit of the conversion result). See Table 3. As long as the voltage on the VIN pin is maintained within the - 0.3V to (VCC + 0.3V) absolute maximum operating range a correct result is generated for any input value from - 0.125 * VREF to 1.125 * VREF. For input voltages greater than 1.125 * VREF the conversion result is clamped to the value corresponding to 1.125 * VREF. For input voltages below - 0.125 * VREF the conversion result is clamped to the value corresponding to - 0.125 * VREF. The output code including the status bits form a uniform monotonic unsigned binary encoding of the analog input value. Digital arithmetic operations can be performed upon the entire 32-bit output without having to eliminate or block out any one of the four status bits.
B27 MSB 0 0 0 1 1 1 1 0 0 0 0 1 1 1 B26 0 0 0 1 1 0 0 1 1 0 0 1 1 1 B25 0 0 0 1 0 1 0 1 0 1 0 1 1 1 B24 1 1 0 1 0 1 0 1 0 1 0 1 0 0 B23 1 1 0 1 0 1 0 1 0 1 0 1 0 0 ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... B0 LSB 1 1 0 1 0 1 0 1 0 1 0 1 0 0
LTC2400
APPLICATIO S I FOR ATIO
Frequency Rejection Selection (FO Pin Connection)
NORMAL REJECTION MODE (dB)
The LTC2400 internal oscillator provides better than 110dB normal mode rejection at the line frequency and all its harmonics for 50Hz 2% or 60Hz 2%. For 60Hz rejection FO (Pin 8) should be connected to GND (Pin 4) or to a LOW logic level while for 50Hz rejection the FO pin should be connected to VCC (Pin 1) or to a HIGH logic level. The selection of 50Hz or 60Hz rejection can also be made during normal operation by an external controller able to drive FO to an appropriate logic level. A selection change during the Sleep or Data Output states will not disturb the converter operation. If the selection is made during the Conversion state the result of the conversion in progress may be outside specifications but the following conversions will not be affected. When a fundamental rejection frequency different from 50Hz or 60Hz is required or when the converter must be synchronized with an outside source the LTC2400 can operate with an external conversion clock. The converter automatically detects the presence of an external clock signal at the FO pin and turns off the internal oscillator. (The frequency fEOSC of the external signal must be at least 2560Hz.) The external clock signal duty cycle is not significant as long as the minimum and maximum specifications for the high and low periods tHEO and tLEO are observed. While operating with an external conversion clock with a frequency fEOSC the LTC2400 provides better than 110dB normal mode rejection in a frequency range fEOSC/2560 4% and its harmonics. The normal mode rejection as a function of the input frequency deviation from fEOSC/2560 is shown in Figure 3. Whenever an external clock is not present at the FO pin the converter automatically activates its internal oscillator and enters the Internal Conversion Clock mode. The LTC2400 operation will not be disturbed if the change of conversion clock source occurs during the Sleep state or during the Data Output state while the converter uses an external serial clock. If the change occurs during the Conversion state the result of the conversion in progress may be outside specifications but the following conversions will not be affected. If the change occurs during the Data
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-60 -70 -80 -90 -100 -110 -120 -130 -140 -12 -8 -4 0 4 8 12 INPUT FREQUENCY DEVIATION FROM fEOSC /2560 (%)
2400 F03
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Figure 3. LTC2400 Normal Mode Rejection When Using an External Oscillator of Frequency fEOSC
Output state and the converter is in the Internal SCK mode, the serial clock duty cycle may be distorted but the serial data stream will remain valid. Digital Signal Levels The LTC2400 digital inputs (FO, CS and SCK in External SCK mode of operation) accept standard logic levels and the internal hysteresis receivers can tolerate edge rates as slow as 100s. In the same time the LTC2400 exceptional accuracy, shared ground pin and very low power supply current demand special considerations when designing the digital interface. The digital output signals (SDO and SCK in Internal SCK mode of operation) are less of a concern because they are not generally active during the Conversion state. A 250A power supply current flowing through the 0.01 resistance of the common ground pin will develop a 2.5V offset signal. For a reference voltage VREF = 2.5V this represents a 1ppm offset error. In order to preserve the LTC2400 accuracy it is very important to minimize the ground path impedance which may appear in series with the input and/or reference signal and to reduce the current which may flow through this path. The GND pin should be connected to a low resistance ground plane through a minimum length trace. The use of multiple via holes is recommended to further reduce the connection resistance.
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LTC2400
APPLICATIO S I FOR ATIO
In an alternative configuration the GND pin of the converter can be the single-point-ground in a single point grounding system. The input signal ground, the reference signal ground, the digital drivers ground (usually the digital ground) and the power supply ground (the analog ground) should be connected in a star configuration with the common point located as close to the GND pin as possible. The power supply current during the Conversion state should be kept to a minimum. This goal can be achieved by restricting the number of digital signal transitions occurring during this period to the minimum necessary. While a digital input signal is in the range 0.5V to (VCC - 0.5V) the CMOS input receiver draws additional current from the power supply. It should be noted that, when any one of the digital input signals (FO, CS and SCK in External SCK mode of operation) is within this range, the LTC2400 power supply current may increase even if the signal in question is at a valid logic level. For micro power operation and in order to minimize the potential errors due to additional ground pin current it is recommended to drive all digital input signals to full CMOS levels [VIL < 0.4V and VOH > (VCC - 0.4V)]. Severe ground pin current disturbances can also occur due to the undershoot of fast digital input signals. Undershoot and overshoot occur because of the impedance mismatch at the converter pin when the transition time of an external control signal is less than twice the propagation delay from the driver to LTC2400. For reference, on a regular FR-4 board the signal propagation velocity is approximately 183ps/inch for internal traces and 170ps/inch for surface traces. Thus a driver generating a control signal with a minimum transition time of 1ns must be connected to the converter pin through a trace shorter than 2.5 inches. This problem becomes particularly difficult when shared control lines are used and multiple reflections may occur. The solution is to carefully terminate all transmission lines close to their characteristic impedance. Parallel termination near the LTC2400 pin will eliminate this problem but will increase the driver power dissipation. A series resistor between 27 and 56 placed near the driver or near the LTC2400 pin will also eliminate this
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problem without additional power dissipation. The actual resistor value depends upon the trace impedance and connection topology. SERIAL INTERFACE The LTC2400 transmits the conversion results and receives the start of conversion command through a synchronous 3-wire interface. During the Conversion and Sleep states this interface is used to assess the converter status and during the Data Output state it is used to read the conversion result. Serial Clock Input/Output SCK The serial clock signal present on SCK (Pin 7) is used to synchronize the data transfer. Each bit of data is driven by SDO (Pin 6) on the falling edge of the serial clock. In the Internal SCK mode of operation the SCK pin is an output and the LTC2400 creates its own serial clock by dividing the internal conversion clock by 8. In the External SCK mode of operation the SCK pin is used as input. The selection between Internal and External SCK operation modes is performed every time a HIGH to LOW transition is detected at the CS pin. If SCK is HIGH during this transition the converter enters the Internal SCK mode. If SCK is LOW during this transition the converter enters the External SCK mode. In order to accommodate the continuous conversion mode in which CS (Pin 5) is permanently tied to GND (Pin 4), the LTC2400 also selects between Internal and External SCK operation modes during power-on reset. At this time an internal pull-up is activated in order to test the state of the SCK pin even if an external driver does not drive this pin. If during the power-on reset phase the CS pin and the SCK pin are kept low, the converter enters the External SCK mode. If during the power-on reset phase the CS pin is LOW and the SCK pin is not externally driven or is kept HIGH, the converter enters the Internal SCK mode. The converter remembers the previously selected Serial Clock mode of operation as long as CS is low. Following a LOW to HIGH transition on CS a new selection must be made on the following CS HIGH to LOW transition. Even if the LTC2400 is in Internal SCK mode the SCK output driver
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LTC2400
APPLICATIO S I FOR ATIO
is enabled only during the Data Output state. During the Conversion and Sleep states, if CS is LOW and the converter is in Internal SCK mode, an internal weak pull-up is activated for the SCK pin. During the same states, if CS is HIGH the internal pull-up is activated only if SCK is already high. Thus, when not externally driven the SCK pin will be kept HIGH by the internal pull-up such that the CS falling edge will select the Internal SCK mode. Figure 4 shows a typical data output sequence in the Internal SCK mode which is selected when, during the falling edge of CS, the SCK pin is HIGH. Following the falling edge of CS the converter drives 32 clock pulses through the SCK pin. On every falling edge of SCK a new data bit is driven at the SDO pin. Figure 5 shows a typical data output sequence in the External SCK mode which is selected when, during the falling edge of CS, the SCK pin is LOW. Following the falling edge of CS the first 32 clock pulses received at the SCK pin are used to shift out the conversion result through the SDO pin.
CS
BIT 31 SDO Hi-Z EOC
BIT 30
BIT 29 SIG
SCK (INTERNAL) SLEEP DATA OUTPUT CONVERSION
2400 F04
Figure 4. Typical Internal SCK Data Output Operation
CS
BIT 31 SDO Hi-Z EOC
BIT 30
BIT 29 SIG
SCK (EXTERNAL) SLEEP DATA OUTPUT CONVERSION
2400 F05
Figure 5. Typical External SCK Data Output Operation
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Serial Data Output SDO The serial data output pin, SDO (Pin 6), is used to drive the serial data during the Data Output state. In addition the SDO pin is used as an end of conversion indicator during the Conversion and Sleep states. In order to enable a shared serial data line configuration, when CS (Pin 5) is HIGH the SDO driver is switched to a high impedance state. Whenever CS is LOW during the conversion phase the SDO pin is driven HIGH to indicate that the current conversion cycle has not yet been completed. Whenever CS is LOW during the sleep phase the SDO pin is driven LOW to indicate that the current conversion cycle has been completed. It is important to notice that the LTC2400 will exit the Sleep state on the first rising edge of SCK occurring while CS is LOW. When operating in the External SCK mode, the end of conversion status can be tested without forcing the conBIT 28 EXR BIT 27 MSB BIT 26 BIT 0 LSB
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BIT 28 EXR
BIT 27 MSB
BIT 26
BIT 0 LSB
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LTC2400
APPLICATIO S I FOR ATIO
verter to enter the Data Output state as long as the SCK pin is maintained LOW during the test (the SCK pin should be already LOW on the falling edge of CS in order to indicate the External SCK mode). The serial interface waveforms corresponding to this situation are shown in Figure 6. The first time CS is driven LOW the SDO signal changes from the HIGH-Z state to HIGH indicating that the conversion is in progress. The second time CS is driven LOW the SDO signal again changes from HIGH-Z to HIGH because the conversion is not yet finished. When the conversion cycle is completed the SDO pin switches from HIGH to LOW indicating the availability of a new conversion result and the LTC2400 enters the Sleep state. As long as the SCK pin is maintained LOW the converter remains in Sleep mode. The third time CS is driven LOW the SDO signal changes from HIGH-Z to LOW indicating a completed conversion. At some point in time the SCK pin is driven from a LOW to a HIGH thus terminating the Sleep state and beginning the Data Output state.
CS
SDO Hi-Z Hi-Z Hi-Z
SCK (EXTERNAL) CONVERSION SLEEP DATA OUTPUT
2400 F06
Figure 6. End of Conversion Test--External SCK Operation
CS
SDO Hi-Z Hi-Z Hi-Z
SCK (INTERNAL) CONVERSION SLEEP DATA OUTPUT
2400 F07
Figure 7. End of Conversion Test--Internal SCK Operation
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When operating in the Internal SCK mode, the end of conversion status can be tested without forcing the converter to enter the Data Output state as long as the CS pin is maintained LOW for a time period less than TEOCtest. TEOCtest is equal with 45% of the Internal SCK period 1/fSCK. If LTC2400 is using the internal oscillator (Pin FO is maintained at a LOW or HIGH logic level) TEOCtest = 23s. If the LTC2400 is using an external oscillator of frequency fEOSC (connected to the FO pin) TEOCtest = 3.6/fEOSC. The serial interface waveforms corresponding to this situation are shown in Figure 7. The first time CS is driven LOW the SDO signal changes from the HIGH-Z state to HIGH indicating that the conversion is in progress. The second time CS is driven LOW the SDO signal again changes from HIGH-Z to HIGH because the conversion is not yet finished. When the conversion cycle is completed the SDO pin switches from HIGH to LOW indicating the availability of a new conversion result and the LTC2400 enters the Sleep state. At this moment, in order to maintain the
BIT 31 EOC BIT 30 BIT 29 SIG W
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LTC2400
APPLICATIO S I FOR ATIO
converter in Sleep mode CS must not remain LOW for longer than TEOCtest. The third time CS is driven LOW the SDO signal changes from HIGH-Z to LOW indicating a completed conversion. After a TEOCtest time interval the SCK pin changes from a LOW to a HIGH thus terminating the Sleep state and beginning the Data Output state. Chip Select Input CS (Figure 8) The active low chip select, CS (Pin 5), is used to test the conversion status and to enable the data output transfer as described in the previous sections. In addition, the CS signal can be used to trigger a new conversion cycle before the entire serial data transfer has been completed. The LTC2400 will abort any serial data transfer in progress and start a new conversion cycle anytime a LOW to HIGH transition is detected at the CS pin after the converter has entered the Data Output state (i.e. after the first rising edge of SCK which occurs while CS = LOW and SDO = LOW). CS (Pin 5) can also be used to control the converter Autostart mode of operation. This configuration is described in Figure 12. After the completion of a conversion the LTC2400 enters the low power Sleep state. The time spent in this state is controlled by an internal 25nA current source which discharges an external capacitor
CS
BIT 31 SDO Hi-Z EOC Hi-Z SDO Hi-Z
SCK (INTERNAL) SLEEP DATA OUTPUT CONVERSION
Figure 8. Data Output Abort
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connected to the CS pin. When this capacitor has been discharged to approximately 1.4V (1.1V for VCC = 3V), the LTC2400 will start the serial data transfer followed by a new conversion cycle. The autostart is particularly useful when combined with the Internal SCK operation mode. The CS waveform in Figure 12 shows the external capacitor charge and discharge cycles. The value of the external capacitor CEXT determines the duration of the sleep cycle. It should be noticed that the external capacitor discharge current is kept very small in order to decrease the converter power dissipation in the Sleep state. In the Autostart mode the analog voltage on the CS pin can not be observed without disturbing the converter operation using a regular oscilloscope probe. When using this configuration it is important to minimize the external leakage current at the CS pin by using a low leakage external capacitor and properly cleaning the PCB surface. CONFIGURATION OPTIONS This section describes the configuration details of the serial interface and conversion cycle control signals for the LTC2400 most significant operating modes. In all these cases the converter can use the internal oscillator (FO = LOW or FO = HIGH) or an external oscillator connected to the FO pin.
CS BIT 31 EOC Hi-Z SCK (EXTERNAL) SLEEP DATA OUTPUT CONVERSION
2400 F08
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LTC2400
APPLICATIO S I FOR ATIO
A summary of the most common configuration options is shown in Table 4. Internal Serial Clock, Continuous Operation (Figure 9) In this configuration the converter creates its own serial clock and operates at the maximum possible conversion rate. Following a conversion the LTC2400 spends only a minimum amount of time in the Sleep state and immediately initiates the data output operation. After all 32 bits of the result are shifted out the converter starts a new cycle. The CS pin is maintained at a LOW logic level. The Internal SCK mode is selected during power-on reset. It is important to ensure that there is no external driver that may be driving the SCK pin LOW during the power-up sequence. An external pull-up device at SCK is not required because the internal weak pull-up device is active. Internal Serial Clock, Single Cycle Operation (Figure 10) In this configuration the converter creates its own serial clock and an external controller driving the CS signal triggers each conversion operation. The LTC2400 enters the Sleep state following every conversion. When CS is driven LOW the converter initiates the data output operation. The CS signal remains low during the entire data output phase and is returned to a high state sometime during the Conversion state. After all 32 bits of the result are shifted out, the LTC2400 starts a new conversion. An external controller can determine if the conversion is completed by driving CS to LOW and monitoring the SDO
Table 4. LTC2400 Configuration Options
SCK Source Internal Internal Internal Internal External External External
Configuration Internal SCK, Continuous Conversion Internal SCK, Single Cycle Conversion Internal SCK, Reduced Data Output Internal SCK, Autostart Conversion External SCK, Continuous Conversion External SCK, Single Cycle Conversion External SCK, Reduced Data Output
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signal. If SDO = LOW a new conversion result is available. If the external controller wants to maintain the LTC2400 in the Sleep state it must limit the time CS is maintained LOW to less than TEOCtest. For exact values of TEOCtest see the Serial Interface, Serial Data Output (SDO) section. The Internal SCK mode is reselected on every falling edge of CS. It is important to ensure that there is no external driver that may be driving the SCK pin LOW during the CS falling edge. In general a pull-up resistor at SCK is not required because the internal weak pull-up device is active. The internal pull-up is disabled when an external driver has pulled SCK LOW while CS is HIGH. If this situation may occur (in a shared SCK configuration for example) and the external driver stops driving the SCK pin (enters a HIGH-Z state) while this pin is LOW the internal pull-up is not available to restore SCK to HIGH before the falling edge of CS. One solution is to control the external driver such that it drives SCK HIGH immediately before entering a HIGH-Z state. A similar problem may occur during the Sleep state when CS is pulsed HIGH-LOW-HIGH in order to test the conversion status. If SDO is LOW (the LTC2400 is in Sleep state) the SCK pin will also be driven LOW in preparation for the Data Output state. When CS is driven HIGH in a time shorter than TEOCtest with the desire to postpone the serial output operation, the SCK driver is turned off and the internal pull-up is activated. For a heavy capacitive load on the SCK pin the internal pull-up may not be adequate to return this line to a HIGH level fast enough. This is not a
Data Output Length 32 Bits 32 Bits 1 to 32 Bits 32 Bits 32 Bits 32 Bits 1 to 32 Bits Conversion Cycle Control Minimum CS CS and CS CEXT SCK CS and SCK CS and SCK Data Output Control Internal CS CS and CS Internal SCK CS and SCK CS and SCK Connection and Waveforms Figure 9 Figure 10 Figure 11 Figure 12 Figure 13 Figure 14 Figure 15
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LTC2400
APPLICATIO S I FOR ATIO
1F
2.7V TO 5.5V
VCC
VREF 0.1V TO 0.9 x VCC VIN -0.12VREF TO 1.12VREF
CS
SDO
BIT 31 EOC
BIT 30
SCK (INTERNAL) CONVERSION SLEEP DATA OUTPUT CONVERSION
2400 F09
Figure 9. Internal Serial Clock, Continuous Operation
2.7V TO 5.5V 1F VCC LTC2400 VREF 0.1V TO 0.9 x VCC VIN -0.12VREF TO 1.12VREF VREF SCK FO
VCC
VIN GND
BIT 31 EOC
BIT 30
SCK (INTERNAL) CONVERSION SLEEP DATA OUTPUT CONVERSION
2400 F10
Figure 10. Internal Serial Clock, Single Cycle Operation
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VCC LTC2400 VREF SCK FO = 50Hz REJECTION = EXTERNAL OSCILLATOR = 60Hz REJECTION VIN GND SDO CS BIT 29 SIG BIT 28 EXR BIT 27 MSB BIT 26 BIT 0 LSB
VCC = 50Hz REJECTION = EXTERNAL OSCILLATOR = 60Hz REJECTION 10k SDO CS BIT 29 SIG BIT 28 EXR BIT 27 MSB BIT 26 BIT 0 LSB Hi-Z Hi-Z
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LTC2400
APPLICATIO S I FOR ATIO
concern if, upon detecting SDO = LOW the CS pin is maintained LOW and a serial data output process is initiated. A solution for both these limit cases is to use an external 10k pull-up resistor on the SCK pin. Internal Serial Clock, Reduced Data Output Length (Figure 11) This mode of operation can be used if the result already stored in the converter is no longer relevant and a new result is required as soon as possible. The Data Output state can be aborted immediately after the first rising edge of SCK and a new conversion can be started with minimum delay. This operation mode can also be used when not all 32 bits of the output stream are required. For example when the external controller needs only the four status bits and the 20 most significant result bits the Data Output state can be interrupted following the 24th rising edge of SCK.
2.7V TO 5.5V 1F VCC LTC2400 VREF 0.1V TO 0.9 x VCC VIN -0.12VREF TO 1.12VREF VREF SCK FO
VIN GND
BIT 0 SDO Hi-Z EOC Hi-Z
BIT 31 EOC
Hi-Z
Hi-Z
SCK (INTERNAL) SLEEP CONVERSION DATA OUTPUT SLEEP DATA OUTPUT CONVERSION
2400 F11
Figure 11. Internal Serial Clock, Reduced Data Output Length
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In this configuration the converter creates its own serial clock and an external controller driving the CS signal triggers each conversion operation. The LTC2400 enters the Sleep state following every conversion. When CS is driven LOW the converter initiates the data output operation. The CS signal must be maintained LOW until the first rising edge of SCK. After that CS is driven HIGH before all 32 bits of the result are shifted out. At this moment the LTC2400 aborts the Data Output state and starts a new conversion. The Internal SCK mode is reselected on every falling edge of CS. It is important to ensure that there is no external driver that may be driving the SCK pin LOW during the CS falling edge. In general a pull-up resistor at SCK is not required because the internal weak pull-up device is active. The internal pull-up is disabled when an external driver has pulled SCK LOW while CS is HIGH. If this situation occurs (in a shared SCK configuration for example) and the
VCC
VCC
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= 50Hz REJECTION = EXTERNAL OSCILLATOR = 60Hz REJECTION
10k
SDO CS
BIT 30
BIT 29 SIG
BIT 28 EXR
BIT 27 MSB
BIT 26
BIT 8
Hi-Z
LTC2400
APPLICATIO S I FOR ATIO
external driver stops driving the SCK pin (enters a HIGH-Z state) while this pin is LOW, the internal pull-up is not available to restore SCK to HIGH before the falling edge of CS. A solution is to control the external driver such that it drives SCK HIGH immediately before entering a HIGH-Z state. A similar problem may occur when CS is pulled HIGH (the Data Output state is terminated) while the converter is driving a LOW on the SCK pin. In this case the internal pullup is again not available to restore SCK to HIGH before the falling edge of CS. This situation can be avoided by driving CS high only following a rising edge of SCK. An alternative solution for these two problems is to use an external 10k pull-up resistor on the SCK pin. Internal Serial Clock, Autostart Operation (Figure 12) In this configuration the converter creates its own serial clock and each conversion operation is triggered by the
2.7V TO 5.5V 1F VCC LTC2400 VREF 0.1V TO 0.9 x VCC VIN -0.12VREF TO 1.12VREF VREF SCK FO
VCC CS GND BIT 31 SDO Hi-Z EOC BIT 30 BIT 29 SIG BIT 0 LSB Hi-Z
SCK (INTERNAL) CONVERSION SLEEP DATA OUTPUT CONVERSION
2400 F12
Figure 12. Internal Serial Clock, Autostart Operation
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internal controlled discharge of an external timing capacitor connected to the CS pin. The LTC2400 enters the Sleep state following every conversion. The time the converter remains in the Sleep state is determined by the value of the external timing capacitor. Specific values are shown in the Typical Performance Characteristics section. The CS capacitor remains discharged during the Data Output state and is automatically recharged during the Conversion state. After all 32 bits of the result are shifted out, the LTC2400 starts a new conversion. The Internal SCK mode is reselected every time the voltage on the CS pin traverses the pin receiver threshold from a high to a low value. It is important to ensure that there is no external driver that may be driving the SCK pin LOW during the CS falling edge. In general a pull-up resistor at SCK is not required because the internal weak pull-up device is active.
VCC
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= 50Hz REJECTION = EXTERNAL OSCILLATOR = 60Hz REJECTION
VIN GND
SDO CS CEXT
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LTC2400
APPLICATIO S I FOR ATIO
External Serial Clock, CS = 0 Operation (Figure 13) In this configuration an external controller using the SCK line only directs LTC2400 operation. Following a conversion the LTC2400 remains in the Sleep state until it detects the first rising edge on the SCK pin. After this event it enters the Data Output state where it remains until it detects 32 falling edges on the SCK pin. At this moment all 32 bits of the result have been shifted out and the converter starts a new cycle. The CS pin is maintained at a LOW logic level. The External SCK mode is selected during power-on reset. It is important to ensure that an external driver is forcing the SCK pin LOW before the end of the power-up sequence. The end of conversion can be detected by monitoring the SDO pin. Following the Data Output state (following the 32nd falling edge of SCK) the SDO pin is HIGH while a new conversion is in progress. As soon as the LTC2400 returns to the Sleep state the SDO pin becomes LOW. An external controller can monitor the voltage on the SDO pin or can
2.7V TO 5.5V 1F VCC LTC2400 VREF 0.1V TO 0.9 x VCC VIN -0.12VREF TO 1.12VREF VREF SCK FO
VCC
CS
BIT 31 SDO EOC
SCK (EXTERNAL) CONVERSION SLEEP DATA OUTPUT CONVERSION
2400 F13
Figure 13. External Serial Clock, CS = 0 Operation
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use it as an interrupt signal to decide when a new conversion result is available. External Serial Clock, Single Cycle Operation (Figure 14) This is the most common configuration for LTC2400. Following a conversion the LTC2400 enters the Sleep state. The converter will remain in this state until it detects the first rising edge of SCK while CS is driven LOW. The CS signal remains low during the entire data output phase and is returned to a HIGH state sometime during the Conversion state. After all 32 bits of the result are shifted out, the LTC2400 starts a new conversion. The External SCK mode is reselected on every falling edge of CS. It is important to ensure that the SCK pin is driven LOW during the CS falling edge. The end of conversion can be detected by testing the SDO pin. Anytime during the Conversion or Sleep states the SDO can be observed after CS is driven LOW.
= 50Hz REJECTION = EXTERNAL OSCILLATOR = 60Hz REJECTION VIN GND SDO CS BIT 30 BIT 29 SIG BIT 28 EXR BIT 27 MSB BIT 26 BIT 1 BIT 0 LSB
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LTC2400
APPLICATIO S I FOR ATIO
1F
2.7V TO 5.5V
VCC
VREF 0.1V TO 0.9 x VCC VIN -0.12VREF TO 1.12VREF
CS TEST EOC SDO Hi-Z Hi-Z TEST EOC
BIT 31 EOC
SCK (EXTERNAL) CONVERSION SLEEP DATA OUTPUT CONVERSION
2400 F14
Figure 14. External Serial Clock, Single Cycle Operation
If SDO = HIGH the conversion is not yet completed. If SDO = LOW a new result is available and the Data Output state can be initiated at any time. External Serial Clock, Reduced Data Output Length (Figure 15) This mode of operation can be used if the result already stored in the converter is no longer relevant and a new result is required as soon as possible. The Data Output state can be aborted immediately after the first SCK rising edge and a new conversion can be started with minimum delay. This operation mode can also be used when not all 32 bits of the output stream are required. For example, when the external controller needs only the four status bits and the 20 most significant result bits the Data Output state can be interrupted following the 23rd falling edge of SCK.
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VCC LTC2400 VREF SCK FO = 50Hz REJECTION = EXTERNAL OSCILLATOR = 60Hz REJECTION VIN GND SDO CS BIT 30 BIT 29 SIG BIT 28 EXR BIT 27 MSB BIT 26 BIT 1 BIT 0 LSB Hi-Z
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Following a conversion the LTC2400 enters the Sleep state. The converter will remain in this state until it detects the first rising edge of SCK while CS is driven LOW. After that CS is driven HIGH before all 32 bits of the result are shifted out. At this moment the LTC2400 aborts the Data Output state and starts a new conversion. The External SCK mode is reselected on every falling edge of CS. It is important to ensure that the SCK pin is driven LOW during the CS falling edge. The end of conversion can be detected by testing the SDO pin. Anytime during the Conversion or Sleep states the SDO can be observed after CS is driven LOW. If SDO = HIGH the conversion is not yet completed. If SDO = LOW a new result is available and the Data Output state can be initiated at any time.
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LTC2400
APPLICATIO S I FOR ATIO
1F
2.7V TO 5.5V
VCC
VREF 0.1V TO 0.9 x VCC VIN -0.12VREF TO 1.12VREF
CS TEST EOC TEST EOC TEST EOC
BIT 0 SDO EOC
BIT 31 EOC
Hi-Z
Hi-Z
Hi-Z
SCK (EXTERNAL) SLEEP CONVERSION DATA OUTPUT SLEEP DATA OUTPUT CONVERSION
2400 F15
Figure 15. External Serial Clock, Reduced Data Output Length
PACKAGE DESCRIPTIO
S8 Package 8-Lead Plastic Small Outline (Narrow 0.150)
(LTC DWG # 05-08-1610)
0.189 - 0.197* (4.801 - 5.004) 0.010 - 0.020 x 45 (0.254 - 0.508) 0.008 - 0.010 (0.203 - 0.254) 0.053 - 0.069 (1.346 - 1.752) 0- 8 TYP 8 0.004 - 0.010 (0.101 - 0.254) 0.228 - 0.244 (5.791 - 6.197) 0.150 - 0.157** (3.810 - 3.988) 7 6 5
0.016 - 0.050 0.406 - 1.270
0.014 - 0.019 (0.355 - 0.483)
*DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE **DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE
RELATED PARTS
PART NUMBER LT1460 LT1236A-5 DESCRIPTION Micropower Series Reference Precision Bandgap Reference, 5V COMMENTS 0.075% Max, 10ppm/C Max Drift, 2.5V, 5V and 10V Versions, MSOP, PDIP, SO-8, SOT-23 and TO-92 Packages 0.05% Max, 5ppm/C Drift
2400p LT/TP 1198 2K * PRINTED IN USA
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Linear Technology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408)432-1900 q FAX: (408) 434-0507 q www.linear-tech.com
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VCC LTC2400 VREF SCK FO = 50Hz REJECTION = EXTERNAL OSCILLATOR = 60Hz REJECTION VIN GND SDO CS BIT 30 BIT 29 SIG BIT 28 EXR BIT 27 MSB Hi-Z BIT 9 BIT 8
0.050 (1.270) TYP 1 2 3 4
SO8 0996
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(c) LINEAR TECHNOLOGY CORPORATION 1998

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